The present invention relates in general to semiconductor technology, and in particular, to increasing the density of trenches for applications such as power Metal Oxide Semiconductor Field Effect Transistors (MOSFETs).
Integrated circuit manufacturers continually strive to increase the number of devices that can be formed across a single wafer. Power MOSFETs, due to their required large gate areas, typically occupy the entire area of a die on a semiconductor wafer. In conventional power MOSFETs, these required large gate areas pose a limit on the number of dies that can be realized per wafer(i.e. "die density"). One way to overcome this limit is to form a trench into the wafer and use its recess to form a three-dimensional gate. A three dimensional gate reduces the two-dimensional surface dimensions of a die (i.e. the "die size") without sacrificing gate area. Power transistors of this type are often referred to in the art as "Power Trench MOSFETs."
A cross-sectional view of a typical trench MOSFET 10, which can be used for power applications, is shown in FIG. 1. It includes an n-type substrate 102 upon which an n-type epitaxial layer (not shown in FIG. 1) is typically grown. The substrate 102 embodies the drain of the trench MOSFET 10. A p-type body layer 108 covers the epitaxial layer. A pair of trenches 100 extend through the body layer 108 and into the epitaxial layer. Dielectric layers 104 are formed on the walls of the trenches 100. The dielectric layers 104 have inner walls facing towards the centers of their respective trenches 100 and outer walls. N+ source regions 10 flank the outer walls of the dielectric layers 104 and extend into the body layer 108. Heavy body regions 112, also within the body layer 108, are positioned between the source regions 110. Conductive layers 106 (e.g., polysilicon) substantially fill the trenches 100 and embody the gate of the trench MOSFET 10. Finally, dielectric caps 114 cover the filled trenches 100 and also partially cover the source regions 110.
During fabrication of the trench MOSFET 10 an anisotropic etch step is typically performed to form the trenches 100. An anisotropic etch is used, as opposed to an isotropic etch, since an anisotropic etch etches substantially in one direction, which in this case, is vertical and downward. The substantially vertical trenches 100 help to maintain the width defined by the trench patterns, a characteristic that is beneficial in maintaining a predetermined distance between the centers of the trenches 100 (i.e., trench pitch).
After the trenches 100 are formed, a rounding etch is typically performed to round corners, which form at the top and bottom of the trenches 100 during the trench etch step. Another step that is typically performed just prior to growing the gate oxide for the trench MOSFET 10, is the growing of a sacrificial oxide, which is grown and then stripped to remove defects from the walls of the trenches.
To increase the trench density, it is desirable to minimize the trench width as well as the trench pitch. However, both of these dimensions are limited by constraints imposed by manufacturing equipment as well as device operational requirements. The minimum reliably manufacturable trench width is generally dictated by the capability of the photolithography equipment. Further, the minimum width of the mesa formed between trenches is defined by the source and heavy body regions and the source contact areas.
What is needed, therefore, is a method that can overcome limitations on the minimum achievable trench width and trench pitch to provide electronic devices, such as trench MOSFETs, with a higher trench density despite limits imposed by minimum lithographic print dimension capabilities, and without violating the minimum allowable mesa width.